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Understanding the Cell Microprocessor

 by Anand Lal Shimpi on March 17, 2005 12:05 AM EST
70 Comments | Add A Comment
70 Comments

Cell’s In-Order Architecture

We have mentioned that both the PPE and SPEs are in-order cores, but in order to understand the impact of an in-order core on performance, there’s a bit of background knowledge that we have to go over first.

Dependencies, Instruction Ordering and Parallelism

What are Dependencies?

In many of our past CPU articles, we’ve brought up this idea of dependencies as seen by the CPU.   At the very basic level, a CPU is fed a stream of instructions that are generally of the form:

OP destination, source1, source2, ... , source n

The instruction format will vary from one CPU ISA to the next, but the general idea is that the CPU is sent an operation (OP), a destination to store the result of the operation, and one or more sources on which to get data to perform the operation.   Depending on the architecture, the destination and sources can be memory locations or registers.   For the sake of simplicity, let’s just assume that for now, all destinations and sources are registers.

Let’s take a look at an example with some data filled in:

ADD R10, R1, R2

The above line of assembly would be sent to the CPU, telling it to add the values stored in R1 (Register #1) and R2 and store the result in R10.   Simple enough.   Now, let’s give the CPU another operation to crunch on:

MUL R11, R10, R3

This time, we’re multiplying the values stored in R10 and R3, and storing the result in R11.   As a single line of assembly, the above code is easily executed, but when placed directly after our first example, we’ve created a bit of a problem:
  1.      ADD R10, R1, R2
  2.      MUL R11, R10, R3
  3.      ADD R9, R11, R4
Line 1 writes to R10, while Line 2 reads from R10.   Under no circumstances can the CPU begin executing line 2 before line 1 completes - the same goes for lines 3 and 2.   What we’ve created here is what is known as a RAW dependency, Read After Write.   There are many more types of dependencies, but understanding this basic example is more than enough to take us to the next topic at hand - the impact of such dependencies.

The problem with a dependency is that it limits what can be executed in parallel.   Take the Athlon 64, for example.  It has three integer execution units, all of which are equally capable of executing the code (in a slightly revised, x86 assembly format, of course) that we used above.   In theory, the Athlon 64 could execute three lines integer operations in parallel at the same time - assuming that no dependencies existed between the operations.   In executing the above code, two of the Athlon 64’s integer execution units would go idle until the first line of code was executed.

Dependencies, such as the simple one that we talked about above, hinder the ability of modern day microprocessors to function to the best of their abilities.   It’s like having three hands, but only being able to clean your room by picking up one item at a time; frustratingly inefficient.

Cell's On-Die Memory Controller In-Order Architectures
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  • WishIKnewComputers - Thursday, March 17, 2005 - link

    Well, I dont really see the Cell 'breaking' in any way. Between being in the PS3, IBM servers/supercomputers, and Sony and Toshiba electronics, the chip will be all over the place.

    As for it showing up in PCs... no it wont happen anytime soon, but I really dont think it's intended to at this point. Workstation and playstations are its main concern, and smartly so. The Cell in its first generation isnt cut out for superior general tasking, obviously, but when those things start pumping out (and they will... the PS2 has sold what, 80 million units?), there will likely be different and more advanced versions. And if some of those are changed for enhanced general purposing somehow or another, then they could have shot at entering the PC world. As for taking on Intel, though... I dont think IBM is even considering that. If I had to guess, if they wanted to be in a PC, they would have OS X adapted to Cell and IBM would have these things in Apples.

    But no matter which way they go, is it me or does IBM seem light-years ahead of Intel? After looking at Intel's future plans, it seems that they are trying to move towards what IBM is doing now. So is the Cell a processor just ahead of its time, or has Intel just gotten behind?

  • AnnihilatorX - Thursday, March 17, 2005 - link

    This article is seriously a kill for a child like me. I appreciate it though. Well done Anandtech

  • ravedave - Thursday, March 17, 2005 - link

    I can't wait to see what devlopers thing of the cell & the SDK's for it. I have a feeling thats what will kill the cell or make it successfull.

  • microbrew - Thursday, March 17, 2005 - link

    "System on a Chip (SoC)"

    What will make or break the Cell is the tools available, especially the operating system and libraries.

    I would like to see what they're doing in terms of marketing the chip to consumer electronics, telecom, military and other embedded applications. I could see the Cell as a viable alternative to the usual mixures of PowerPcs, ARMs and DSPs.

    I also agree with Final Words; I don't see the Cell breaking into the consumer PC market any time soon either.

  • Locut0s - Thursday, March 17, 2005 - link

    #17 Yeah that was a bit too harsh I agree.

  • Eug - Thursday, March 17, 2005 - link

    I'm just wondering how well a dual-core PPE-based 4+ GHz chip would do in general purpose (desktop) code.

    And I also wonder how cool/hot such a chip would be. The Xbox 2's CPU is probably a 3-core PPE, but it runs at 3 GHz, and we don't have power specs for it anyway.

  • Filibuster - Thursday, March 17, 2005 - link

    #11 (well, everyone should if they haven't before) read the Arstechnica article on PS2 vs PC - static applications vs dynamic media. Cell is taking it to the next level.

    http://arstechnica.com/articles/paedia/cpu/ps2vspc...

    Very nice article Anand!

  • Googer - Thursday, March 17, 2005 - link

    Besides a release date, is there any news or knowledge of a Linux Kit for Playstation 3 like there was for PS2? Does anyone KNOW OF Either?

  • Illissius - Thursday, March 17, 2005 - link

    Damn. Awesome article. If I hadn't known the site and author beforehand, I would've guessed Ars and Hannibal. Seems he isn't the only one with a talent for these kinds of articles ;)
    You should do more of them.

  • scrotemaninov - Thursday, March 17, 2005 - link

    #22: This is just a guess so don't rely on this. The POWER5 has 2way SMT. Each cycle it fetches 8 instructions from the L1I cache. All instructions fetched per cycle are for the same thread so it alternates (round robin). It also has capabilities for setting the thread priority so that you effectively run with 1 thread and it just fetches 8 instructions per cycle for the one running thread.

    I would expect the PPE to be similar to this, fetching 2 instructions for the same thread each cycle. The POWER5 has load balancing stuff in there too - if one thread keeps missing in L2 then the other thread gets more instructions decoded in order to keep the CPU functional unit utilisation up. I've no idea whether this kind of stuff has made it over into the PPE, I'd be a little surprised if it has, especially seeing as this is in-order anyway so it's not like you're going to be aiming for high utilisations rates.
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