Barcelona Architecture: AMD on the Counterattack
by Anand Lal Shimpi on March 1, 2007 12:05 AM EST- Posted in
- CPUs
A Faster Memory Controller
When AMD integrated a memory controller on-die, we knew that every time we saw a new AMD processor, we'd get a slightly enhanced memory controller. In Barcelona, the tweaks are significant and should provide for a tangible improvement in memory performance.
One strength of Intel's FB-DIMM architecture used in Xeon servers is that you can execute read and write requests to the AMB simultaneously. With standard DDR2 memory, you can do one or the other, and there's a penalty for switching between the two types of operations. If you have a fairly random mixture of reads and writes you can waste a lot of time switching between the two rather than performing all of your reads sequentially then switching over to writes. The K8's memory controller made some allowances for preferring reads over writes since they take less time, but in Barcelona the memory controller is far more intelligent.
Now, instead of executing writes as soon as they show up, writes are stored in a buffer and once the buffer reaches a preset threshold the controller bursts the writes sequentially. What this avoids is the costly read/write switch penalty, helping improve bandwidth efficiency and reduce latency.
The K8 core (Socket-940/939/AM2) featured a single memory controller that was 128-bits wide, but in Barcelona AMD has split up the DRAM controller into two separate 64-bit controllers. Each controller can be operated independently and thus you get some improvements in efficiency, especially when dealing with quad core implementations where the individual cores working on independent threads all have their own memory access patterns.
Barcelona's Northbridge is also set up to handle higher bandwidth than before. Deeper buffers are present, allowing for higher bandwidth utilization, and the Northbridge itself is ready for use with future memory technologies (e.g. DDR3). We'd expect one or two revisions past Barcelona will be when AMD switches memory technologies, but the new core will initially debut with DDR2 support.
When AMD integrated a memory controller on-die, we knew that every time we saw a new AMD processor, we'd get a slightly enhanced memory controller. In Barcelona, the tweaks are significant and should provide for a tangible improvement in memory performance.
One strength of Intel's FB-DIMM architecture used in Xeon servers is that you can execute read and write requests to the AMB simultaneously. With standard DDR2 memory, you can do one or the other, and there's a penalty for switching between the two types of operations. If you have a fairly random mixture of reads and writes you can waste a lot of time switching between the two rather than performing all of your reads sequentially then switching over to writes. The K8's memory controller made some allowances for preferring reads over writes since they take less time, but in Barcelona the memory controller is far more intelligent.
Now, instead of executing writes as soon as they show up, writes are stored in a buffer and once the buffer reaches a preset threshold the controller bursts the writes sequentially. What this avoids is the costly read/write switch penalty, helping improve bandwidth efficiency and reduce latency.
The K8 core (Socket-940/939/AM2) featured a single memory controller that was 128-bits wide, but in Barcelona AMD has split up the DRAM controller into two separate 64-bit controllers. Each controller can be operated independently and thus you get some improvements in efficiency, especially when dealing with quad core implementations where the individual cores working on independent threads all have their own memory access patterns.
Barcelona's Northbridge is also set up to handle higher bandwidth than before. Deeper buffers are present, allowing for higher bandwidth utilization, and the Northbridge itself is ready for use with future memory technologies (e.g. DDR3). We'd expect one or two revisions past Barcelona will be when AMD switches memory technologies, but the new core will initially debut with DDR2 support.
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R3MF - Thursday, March 1, 2007 - link
thanks.a 2.4GHz Agena on an AM2+ mATX motherboard, sat in a tiny SUGO 03 case sounds like a very tempting proposition later on this year.
Macuser89 - Thursday, March 1, 2007 - link
Is it just me or is this article saying that AMD is copying a lot of intel's advancements. Great in depth article AT.Le Québécois - Thursday, March 1, 2007 - link
I may be wrong but I think that new CPU or GPU technologies are planned years ahead so for me it look more like they came down to the "same" conclusion on how to improve their CPU. Only Intel did it 1 year before AMD.JarredWalton - Thursday, March 1, 2007 - link
There are fundamentally only so many ways to improve processor performance, and Intel used most of them with Core 2. That AMD is using similar patterns (more buffers, better branch prediction, wider execution, etc.) isn't at all surprising. Just because the same basic principles are used, however, doesn't mean that at the transistor level there aren't significant differences and challenges to overcome.archcommus - Thursday, March 1, 2007 - link
Another great article that displays all the reasons why I read AT - lengthy, technical reviews written by educated authors that are interesting to read and to top it off, with no typing errors! I'm sure you guys use voice software to write these mammoths.I was waiting for details on Barcelona for so long and this is finally it. I have no doubt that AMD will be up to par with Intel again, but the question is, will this significantly SURPASS Core 2 offerings at the time? I hope so but it's not a definite thing yet.
The best thing is, I'm a ways into my computer engineering degree now so I can actually understand a lot of these very techincal articles!
Le Québécois - Thursday, March 1, 2007 - link
You said:But isn't it the same thing?
I mean mid-2007 is the 1st of july and Q3 also begins with july. Could you be more specific? Maybe the month we can expect them?
JarredWalton - Thursday, March 1, 2007 - link
Q3 means anywhere between July and late September, while mid-2007 means June or July time frame. As the official launch date approaches, we'll refine things where possible.Le Québécois - Thursday, March 1, 2007 - link
Thank you for your quick reply, as usual.mjrpes3 - Thursday, March 1, 2007 - link
Any word on when the desktop variant of Barcelona (Agena) will find its way into consumer's hands?puffpio - Thursday, March 1, 2007 - link
When you refer to DDR3 you call it DDDR3unless...there is a DDDR3 I don't know about?