Barcelona Architecture: AMD on the Counterattack
by Anand Lal Shimpi on March 1, 2007 12:05 AM EST- Posted in
- CPUs
A Faster Memory Controller
When AMD integrated a memory controller on-die, we knew that every time we saw a new AMD processor, we'd get a slightly enhanced memory controller. In Barcelona, the tweaks are significant and should provide for a tangible improvement in memory performance.
One strength of Intel's FB-DIMM architecture used in Xeon servers is that you can execute read and write requests to the AMB simultaneously. With standard DDR2 memory, you can do one or the other, and there's a penalty for switching between the two types of operations. If you have a fairly random mixture of reads and writes you can waste a lot of time switching between the two rather than performing all of your reads sequentially then switching over to writes. The K8's memory controller made some allowances for preferring reads over writes since they take less time, but in Barcelona the memory controller is far more intelligent.
Now, instead of executing writes as soon as they show up, writes are stored in a buffer and once the buffer reaches a preset threshold the controller bursts the writes sequentially. What this avoids is the costly read/write switch penalty, helping improve bandwidth efficiency and reduce latency.
The K8 core (Socket-940/939/AM2) featured a single memory controller that was 128-bits wide, but in Barcelona AMD has split up the DRAM controller into two separate 64-bit controllers. Each controller can be operated independently and thus you get some improvements in efficiency, especially when dealing with quad core implementations where the individual cores working on independent threads all have their own memory access patterns.
Barcelona's Northbridge is also set up to handle higher bandwidth than before. Deeper buffers are present, allowing for higher bandwidth utilization, and the Northbridge itself is ready for use with future memory technologies (e.g. DDR3). We'd expect one or two revisions past Barcelona will be when AMD switches memory technologies, but the new core will initially debut with DDR2 support.
When AMD integrated a memory controller on-die, we knew that every time we saw a new AMD processor, we'd get a slightly enhanced memory controller. In Barcelona, the tweaks are significant and should provide for a tangible improvement in memory performance.
One strength of Intel's FB-DIMM architecture used in Xeon servers is that you can execute read and write requests to the AMB simultaneously. With standard DDR2 memory, you can do one or the other, and there's a penalty for switching between the two types of operations. If you have a fairly random mixture of reads and writes you can waste a lot of time switching between the two rather than performing all of your reads sequentially then switching over to writes. The K8's memory controller made some allowances for preferring reads over writes since they take less time, but in Barcelona the memory controller is far more intelligent.
Now, instead of executing writes as soon as they show up, writes are stored in a buffer and once the buffer reaches a preset threshold the controller bursts the writes sequentially. What this avoids is the costly read/write switch penalty, helping improve bandwidth efficiency and reduce latency.
The K8 core (Socket-940/939/AM2) featured a single memory controller that was 128-bits wide, but in Barcelona AMD has split up the DRAM controller into two separate 64-bit controllers. Each controller can be operated independently and thus you get some improvements in efficiency, especially when dealing with quad core implementations where the individual cores working on independent threads all have their own memory access patterns.
Barcelona's Northbridge is also set up to handle higher bandwidth than before. Deeper buffers are present, allowing for higher bandwidth utilization, and the Northbridge itself is ready for use with future memory technologies (e.g. DDR3). We'd expect one or two revisions past Barcelona will be when AMD switches memory technologies, but the new core will initially debut with DDR2 support.
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johnsonx - Saturday, March 3, 2007 - link
Actually that's the new Double-Dog-Dare RAM-3.JarredWalton - Thursday, March 1, 2007 - link
Crazy D's... they're like rabbits!AkumaX - Thursday, March 1, 2007 - link
Great read. I love Anand's articles. We'll see what the future holds, for both AMD and IntelMAME - Thursday, March 1, 2007 - link
I wonder how much market share AMD will lose until this chip become readily available.tuteja1986 - Thursday, March 1, 2007 - link
None... AMD will loose no marketshare. They are in bloody price war... Intel hasn't really regained any lost territory. But Intel have the advantage of performance is trying to find a breakthrough in AMD market share to retake back the lost territory. AMD is still selling everything they make but at huge looses caused by the price war.Griswold - Thursday, March 1, 2007 - link
Huge loses? Do you mistake the loss of Q406 due to the ATI purchase as a loss due to selling under production costs?Phynaz - Thursday, March 1, 2007 - link
Seen that AMD cach flow recently?TwistyKat - Thursday, March 1, 2007 - link
...you have people like me who won't buy anything from Intel. If we didn't have AMD to make Intel competitive we would never have the range of choices we have today. We'd all be running monster Itanics with massive electricity bills.Intel has the resources to effectively put AMD out of business over time if it so chooses, and today I suspect they are focused on something close to that.
fitten - Thursday, March 1, 2007 - link
Won't happen. In order to avoid anti-trust lawsuits, Intel will give AMD money to keep them afloat before they'll allow AMD to fail.
GoatMonkey - Friday, March 2, 2007 - link
If AMD were to be purchased by a larger corporation, like IBM, it would leave Intel free to beat AMD down with all of their resources. Of course, at that point AMD would have the resources of IBM behind it and could potentially fight back better.